PLL for Microwave
Local Oscillators
By David K Minchin VK5KK
Completed KK048 PCB 100 x 65mm
The PLL has been designed for use with 5th or 7th overtone crystal oscillators in the range of 70 to 116 MHz. It uses a 5 to 15 MHz Reference Oscillator, a frequency multiplier, a mixer, two programmable BCD dividers and a phase detector with lock detect.
The circuit has been based on the circuit developed by Dave Glawson, WA6CGR (SBMS, Microwave Update 1994) originally for use with US surplus Microwave "Brick" Oscillators. The circuit has been adapted (simplified) in various areas to suit typical multiplier LO's (e.g. KK7B or G4DDK series) and common crystal frequencies in round figures (see table one below).
For Kits and/or PCB's please Email me or look for details on the Equipment Supplies Web site.
CIRCUIT DESCRIPTION
The circuit is based on a hi-speed CMOS 74HCT7046AN (from Harris) low power PLL chip used as the phase comparator and lock detect circuit. The 74HCT7046AN contains both Type 1 and Type 2 phase detectors, the internal VCO circuit is not used. The Type 2 detector is used as this type uses the leading edge of each of the squared input signals, making signal duty cycle irrelevant. This detector has better immunity to "harmonic" triggering, simplifying the rest of the PLL circuit.
The 74HCT7046AN produces a linear voltage output of 0-5 volts depending on the phase difference of the input signals. This analog signal is fed to the VCXO via a low pass filter, setting the loop response time as well as filtering out the reference divider frequency. The latter function is not as critical as in PLL systems that are required to lock a Free Running VCO's, thanks to the limited frequency range that a crystal oscillator (VCXO) can be pulled.
The stability of the system is entirely dependent upon the quality of the reference oscillator. Some 10 MHz OCXO's (Oven type) available, have a stability in the order of 0.01 ppm or 100 cycles at 10 GHz. The PLL could also be locked to a High accuracy Frequency Counter Reference or one locked to ABC TV Sync pulses. It is also possible to use a high quality Temperature Compensated Crystal Oscillator (TCXO); the stability of commercially available units is usually from 0.1 to 1 ppm. (1 ppm = 10 KHz @ 10 GHz).
The reference oscillator is changed to a HCMOS compatible squarewave through two 74HC04 HCMOS gates. This signal is then fed to the reference frequency "M" divider, consistiong of two 74HCT162AN's. The Reference oscillator is also buffered then fed to a 2N5770 (or sim.) multiplier. The collector of this multiplier can be tuned from 70 to 116 MHz. A 15-pF capacitor is used for 70-90 MHz with a Ferrite cored S18 coil. A 15-pF capacitor is used for 90-110 MHz and a 12-pF capacitor for 110-120 MHz with Aluminium cored S18 coil. The multiplier output is coupled to the LO port of a Mini-Circuits SBL-1 Double balanced mixer.
Any Standard Oscillator e.g. a KK7B or G4DDK/EME33 can be used with this PLL. Sampled output from the Crystal oscillator, in the LO, is amplified to ~7dbm by MAR3 or similar MMIC amplifier before being coupled to the RF input of the mixer. Both the MMIC and the SBL1 mixer provide a significant amount of reverse isolation to prevent the difference frequency (overtone oscillator minus the multiplier frequency) from modulating the Local oscillator.
The SBL-1 mixer provides a baseband "difference" signal at its IF port. For example, in a 10 GHz transverter the Local oscillator may use a crystal on 106.500 MHz. (When multiplied by 96, this becomes 10.224 GHz plus 144 MHz = 10.368 GHz). The SBL-1 mixes the 106.500 MHz overtone oscillator signal with the 100 MHz Harmonic of the reference oscillator (selected by L3/15 pF) producing the difference frequency of 6.5 MHz.
A second 2N5770 (or sim.) amplifies the IF signal, its collector is tuned to the difference frequency by a 100pF Trimmer and L4. The 6.5 MHz is then squared by two 74HC04 gates before being applied to the difference or 'N' divider (two of 74HCT162AN's).
PROGRAMMING
Typical programming of the presettable BCD synchronous counters can be obtained from the Table One, below, listing some of the more common LO crystal frequencies. Other "M" & "N" divisors can be calculated. As the Phase detector will work to about 24 MHz, the "M" reference counter can be set to any value between 2 & 100.
Table One
| L.Osc Freq | "Diff" Freq. | Ref. Freq. | Phase Ref. Freq. | N | M |
| 78 MHz | 8 MHz | 10 MHz | 200KHz | 40 | 50 |
| 92 MHz | 2 MHz | 10 MHz | 200KHz | 10 | 50 |
| 94 MHz | 4 MHz | 14.4 MHz | 200KHz | 20 | 72 |
| 94.8 MHz | 4.8 MHz | 10 MHz | 200KHz | 24 | 50 |
| 96 MHz | 6 MHz | 10 MHz | 200KHz | 30 | 50 |
| 99.6 MHz | 9.6 MHz | 10 MHz | 200KHz | 48 | 50 |
| 103.5 MHz | 3.5MHz | 10 MHz | 500KHz | 7 | 20 |
| 106.5 MHz | 6.5 MHz | 10 MHz | 500KHz | 13 | 20 |
| 116 MHz | 6 MHz | 12 MHz | 200 KHz | 30 | 60 |
For an example, lets take a 99.6 MHz local oscillator. The reference frequency of 10 MHz will be divided by "M" = 50 to give a 200KHz signal to the phase detector. The difference frequency of 9.6 MHz will be divided by "N" = 48 to give a corresponding 200KHz signal.
The counters are then programmed as follows:
The"M" counter division ratio is "50". Subtract this number from 100 and the resultant number is the BCD counter preset number "50".
The Most Significant Digit (M. S .D. 10's Digit), U4 the bottom RHS 74HC162, is then programmed for the BCD number "5" so it is necessary is to ground pins 4 & 6. U3 the bottom LHS 74HC162 (L.S.D. 1's Digit) is programmed with a BCD "0" so ground pins 3,4, 5 and 6.
The"N" counter division ratio is "48". Subtract this number from 100 and the resultant number is the BCD counter preset number "52".
The Most Significant Digit (M. S .D. 10's Digit), U2 the top RHS 74HC162, is then programmed for the BCD number "5" so it is necessary is to ground pins 4 & 6. U1 the top LHS 74HC162 (L.S.D. 1's Digit) is programmed with a BCD "2" so ground pins 3,5,6.
Remember grounding =0, open = 1 (5 Volts via pullup resistors)
CONSTRUCTION NOTES
Overlay of KK048 PCB
Assemble components onto the PCB in any order, leaving the 74HC IC's to last. Normal electrostatic pre-cautions apply for these CMOS IC's. Note the orientation of the SBL1 mixer (Blue dot is Pin #1). The 10 K SIP resistors supplied will require the last two "sections" cut off. Locate the end opposite to the common end (marked with a dot) and cut the body between the 2nd and 3rd. Pins with a sharp pair of side cutters. After doing this, also cut the pin off immediately adjacent to the common pin (not required). This will leave a 4 x 10K terminating resistor. If you can't find SIP resistors, just use four 10k 1/4w resistors mounted vertically with the common terminated in the %V pad to the left (Pin 1 on each 74HC162)
Note 74HC and 74HCT type IC's can be interchanged, in some cases the former are no longer available
2 RFC's (0.3uH) 10 Turns of 0.3ECW close wound on a 3mm air former. Not critical!
L1 For 70 - 120 MHz operation use a Toko S18 Coil (5.5 turns). Use Aluminium Core above 90MHz, a Ferrite Core for below 90 MHz. Note you may have to adjust the 15pF capacitor to tune the correct harmonic in some cases.
L2 For a 4 - 7 MHz range use 35Turns 0.3ECW on a T50-2 Core. Add or subtract turns to raise or lower tuning range in conjunction with C1.
MODIFYING THE LOCAL OSCILLATOR
Solder one end of a 4.7 pF capacitor to the point indicated on the drawing for the Butler or KK7B oscillator. Attach a BB405 (or similar) Varicap from the other end of the 4.7 pF capacitor to ground. At this same point, attach a 10k resistor to the VCO tune output on the PLL PCB via a 1nF-feedthru or bypass capacitor.
After installing the above parts, warm up the oscillator for 10 - 15 minutes with +2.0 volts connected to the 10K resistor. Adjust the Centre frequency of the oscillator to the exact frequency desired. In normal operation the Crystal will start cold at a higher VCO tuning voltage. In some cases it may be necessary to set the final Voltage point to a higher or lower point according to how the oscillator reacts to temperature excursions.
TUNING UP THE PLL PCB
After adjusting the local oscillator, connect the PLL system as per its final configuration. Turn the power on. You should see the Lock LED light up, indicating that the PLL is out of lock. The PLL system is adjusted by connecting an oscilloscope to the collector of the difference amplifier (The second 2N5770 amplifier/L4). Tune L3 to the Harmonic of the Ref oscillator below the Local Oscillator. A frequency counter may help, connected to the LO input of the SBL1 mixer. Typically, L3 is only required to reject the unwanted harmonics by >10 db to ensure correct operation.
C1 and R1 are then tuned for maximum sine wave amplitude at the difference frequency. At some point the Lock LED should extinguish. You can then monitor the VCO tune voltage to confirm that it is somewhere around the point originally adjusted to (~2Volts). Some adjustment may be necessary to the coils if you have departed from the nominal 4 - 7 MHz difference frequency. (~500KHz lowest Freq.)
Once you have lock, adjustment of each control will be seen to be broad due to the capture effect of the 74HC04 Gates. Do not try and judge the "peak" from the LED as you may end up with each circuit being off tune and only just working. You can check the VCO lock range by monitoring the VCO tune voltage and placing you finger on the Local Oscillator coil. You should see the VCO voltage swing, with no change to the Local Oscillator frequency. At some point you should be able to light the LED. Typically the PLL will counteract excursions of +or- 5 KHz. To extend this range, increase the 4P7 coupling capacitor used from the BB405 Varicap.
The PLL is ready for service. The Lock LED should only flash as power is connected to the system. If your Local Oscillator has chronic drift, it may take a few seconds to drift into the lock range. Tests done with cheap 5th overtone crystals, however, produced locks within a second from 10 - 40 degrees C. The final VCO voltage setting will depend on the Local Oscillator's reaction to temperature.
Copyright David Minchin VK5KK 1998